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1 ? summit microelectronics, inc. 1999 2024 9.0 8/8/00 characteristics subject to change without notice summit microelectronics, inc. summit microelectronics, inc. ? 300 orchard city drive, suite 131 campbell, ca 95008 telephone 408-378- 6461 fax 408-378-6586 www.summitmicro.com features ? full voltage control for hot swap applications ? card insertion detection ? platform voltage detection ? card voltage sequencing ? 5 volt, 12 volt and 3.3 volt 12 volt fet enable outputs ? allows use of low on-resistance n-channel fets card reset generation based on out of spec voltages ? host reset programmable slew rate control [250v/sec default rate] supports 5 volt, 3.3 volt and mixed voltage cards integrated 1k bit e 2 prom memory data download? mode [simplifies downloading of configuration memory into interface asic or mcu] hot swap voltage controller s39421 description the s39421 is a fully integrated hot swap controller intended for use on add-in cards that may be inserted into or removed from powered-on host platforms. the s39421 performs a variety of tasks starting with the validation of proper card insertion and the presence of ?in-spec? volt- ages at the host platform interface. once power is switched on, the s39421 continues to monitor the back-end power to the add-in card and the host power supply. if either the 5v or 3.3v supplies drop below vtrip the s39421 will immediately assert the re- set outputs and power-down the add-in card. in addition to the power control for the add-in card, the s39421 provides status signals that can be employed by the host and for the control of bus interface components. the on board e 2 prom can be used as configuration memory for the individual card or as general purpose memory. the proprietary datadownload mode provides a more direct interface to the e 2 prom for simplified access by the add-in card?s controller or asic. functional block diagram + + - - eeprom memory array slew rate control vgate3 vgate5 cs sk di do card_3v card_5v + - + - islew pnd1 pnd2 drvren sgnl_vld reset reset vcc5 vcc3 hst_pwr vsel vcc12 dd filter reset timer sequencing logic hst_rst 2024 ill2.1 card_v_vld associate member
2 s39421 2024 9.0 8/8/00 pin configuration symbol pin description vcc12 1 12 volt input drvren 2 high side driver enable (l) islew 3 slew rate control vsel 4 voltage select dd 5 data download enable cs 6 microwire chip select sk 7 microwire serial clock di 8 microwire data in do 9 microwire data out pnd2 10 pin detect 2 (active low) pnd1 11 pin detect 1 (active low) gnd 12 ground card_v_vld 13 card voltage valid sgnl_vld 14 signals valid (active low) hst_pwr 15 host power up enable hst_rst 16 host reset (active low) reset 17 reset(active low) reset 18 reset card_3v 19 card ? s 3 volt monitor input vgate3 20 3 volt gate output vcc3 21 3 volt input card_5v 22 card ? s 5 volt monitor input vgate5 23 5 volt gate output vcc5 24 5 volt input 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vcc5 vgate5 card_5v vcc3 vgate3 card_3v reset reset hst_pwr sgnl_vld gnd pnd1 pnd2 vcc12 drvren islew vsel dd cs sk di do hst_rst 2024 ill1.1 card_v_vld 2024 pgm t1.1 condition min max temperature -40 c +85 c v cc 2.7v 5.5v recommended operating conditions
s39421 3 2024 9.0 8/8/00 absolute maximum ratings* temperature under bias -55 c to +125 c storage temperature -65 c to +150 c voltage on : drvren vcc12 15v vcc3 7v card_5v 7v card_3v 7v sgnl_vld, card_v_vld & reset 12v reset v cc +.7v all others v cc +.7v output short circuit current 100ma lead solder temperature (10 secs) 300 c comment stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. 2024 pgm t2.3 symbol parameter conditions min typ max units i cc1 power supply current resets active, vgates ramping .6 1 ma i cc2 power supply current quiesent - resets released, vgates on 250 500 a i cc3 power supply current quiesent - eeprom access .8 1.5 ma v trip vtrip sense levels vcc5 and card_5v 4.5 4.6 4.75 v low to high vcc3 and card_3v 2.8 2.9 3.0 v high to low vcc5 and card_5v 4.5 4.70 v vcc3 and card_3v 2.8 2.95 v v trhst trip point hysteresis 7 mv i li input leakage current 1 2 a i lo output leakage current 2 10 a v il input low voltage -0.1 0.8 v v ih input high voltage 2 vcc+1 v v ol output low voltage v cc = 5.0v, i ol = 2.1ma 0.4 v v oh output high voltage v cc = 5.0v, i oh = -400a 2.4 v v olrs reset output low voltage i ol = 3.2ma 0.4 v v ohrs reset output high voltage i oh = -800 a v cc -.75v v dc operating characteristics (over recommended operating conditions)
4 s39421 2024 9.0 8/8/00 symbol parameter conditions min max units t css cs setup time 50 ns t csh cs hold time 0 ns t dis di setup time 100 ns t dih di hold time 100 ns t pd1 output delay to 1 250 ns t pd0 output delay to 0 250 ns t hz output delay to hi-z 100 ns t ew program/erase time 10 ms t csmin minimum cs low time 250 ns t skhi minimum sk low time 250 ns t sv output delay to status valid 250 ns sk max maximum clock frequency 1 mhz memory ac operating characteristics (over recommended operating conditions) 2024 pgm t3.1 symbol parameter notes min typ max units t slew slew rate 250 280 v/sec t hse high side enable delay card insertion noise filter 100 140 200 ms v trhst trip point hysteresis 7 mv t purst power-up reset timeout 105 130 200 ms v rvalid reset output valid 1 .9 v t gltich glitch reject pulse width 40 ns t lvvg loss of voltage to v gate off w. 100 pf load 2 s t lvsv loss of voltage to signal valid off 5 s t lvde loss of voltage to drive enable off 20 s t rpd v trip to reset output delay 5 s t crvg card removal to v gate off w. 100 pf load 2 s t crsv card removal to signal valid off 5 s t crde card removal to drive enable off 20 s sequencer ac operating characteristics (over recommended operating conditions) 2024 pgm t4.4
s39421 5 2024 9.0 8/8/00 reset reset pnd1+pnd2 card_5v & card_3v sgnl_vld t purst t slew t hse 12v level 2024 ill3.1 card_v_vld drvren v card3 & v card5 v trip5 v rvalid v cc5 v gate5 & v gate3 figure 1. card insertion and host reset timing diagram hst_rst [input] tpurst 2024 ill31.0 reset [output]
6 s39421 2024 9.0 8/8/00 figure 3. card removal timing sequence figure 2. loss of voltage timing sequence vcc5 card5v 2024 ill4.2 card_v_vld & reset trpd tlvde tlvsv tlvvg 12v drven sgnlvld vgate5 & vgate3 12v 2024 ill5.2 sgnl_vld vgate5 & vgate3 vcc5 pind1+pind2 tcrvg tcrsv tcrde drven
s39421 7 2024 9.0 8/8/00 pin descriptions pin name [ compactpci name] (pin #) vcc12 (pin 1): supplies the 12 volts required for power- ing the high-side drivers. drvren (pin 2): open drain, active low output indicates the status of the 3 volt and 5 volt high side driver outputs (vgate5 and vgate3). this signal may also be used as a switching signal for the 12 volt supply. islew (pin 3): diode-connected nfet input may be used to adjust the 250v/s default slew rate of the high-side driver outputs. one quarter of the current injected into this pin will be mirrored into each of the high-side driver outputs. vsel (pin 4): ttl level input used to determine which of the host power supply inputs will be monitored for valid voltage and reset generation. vsel-voltage host voltage select monitored low 5 volt or mixed-mode high 3.3 volt only dd (pin 5): a high going edge on this input will place the embedded memory into data download mode. this mode allows the entire contents of the e 2 prom array to be read out of the device by selecting the device (cs high) and providing clock cycles on the sk input. data down- load mode is exited when chip select is brought low. cs (pin 6): e 2 prom memory chip select, active high. sk (pin 7): e 2 prom memory serial clock input. di (pin 8): e 2 prom memory data input. do (pin 9): e 2 prom memory data output. pnd2 [bd_sel2#] (pin 10): active low ttl level input with internal pull-up to vcc5. in conjunction with pnd1, this signal indicates proper card insertion. this pin must be connected to ground on the host side of the connector. pnd1 and pnd2 must be placed on opposite corners of the connector and will preferably be staggered shorter than the power connector pins. board insertion is as- sumed when pnd1 and pnd2 are low. pnd1 [bd_sel1#] (pin 11): active low ttl level input with internal pull-up to vcc5. in conjunction with pnd2, this signal indicates proper card insertion. gnd (pin 12): ground. card_v_vld (pin13): card_v_vld is an open drain output, indicating the card side voltages are at or above v trip . sgnl_vld (pin 14): signals valid (sgnl_vld) is an open drain active low signal indicating the card side power is valid and that the reset signals have been released. this signal can be used by the host as an indication that the bus interface is active and all signals are valid. hst_pwr (pin15): the host power (hst_pwr) input is an active high input. it provides the host system active control over the sequencing of the power up operation. when low, the s39421 will hold the add-in card in reset and block all power to the backend logic. when hst_pwr is high the power sequencing will begin imme- diately and the reset outputs will be driven active after t purst . hst_rst [pci_rst#] (pin 16): ttl level input used as a reset input signal from the host interface. an active low level longer than 40 nsec will cause a reset sequence to be performed on the card. the power switching logic will not be affected. reset (pin 17): reset is an active low open-drain output. it should be tied high through a pull-up resistor connected to v cc . reset (pin 18): reset is an active high open drain (pfet) output. it should be tied low through a pull-down resistor connected to ground. card_3v (pin 19): 3.3 volt card side supply input. this input is monitored for power integrity. if it falls below the 3.3v sense threshold, the pwr_vld signal is de-as- serted and a reset sequence initiates. vgate3 (pin 20): slew rate limited high side driver output for the 3.3v external power fet gate. vcc3 (pin 21): 3.3 volt host side supply input. this input is monitored for power integrity. if it falls below the 3.3v sense threshold, the sgnl_vld signal is de-asserted and the high side drivers disabled. card_5v (pin 22): 5 volt card side supply input. this input is monitored for power integrity. if it falls below the 5v sense threshold and the vsel input is low, the pwr_vld signal is de-asserted and a reset sequence initiates. vgate5 (pin 23): slew rate limited high side driver output for the 5v external power fet gate. vcc5 (pin 24): power to the s39421 and 5 volt host side supply input. this input is monitored for power integrity. if it falls below the 5v sense threshold and the vsel input is low, the sgnl_vld signal is de-asserted and the high side drivers disabled.
8 s39421 2024 9.0 8/8/00 device operation power-up sequence a sequencing operation is initiated by the physical inser- tion of the card into the platform ? s connector. the s39421 ? s vcc5 pin should be connected to the early power pins of the connector. as soon as power is applied, the s39421 will drive the reset outputs active and clamp the vgate outputs to ground. proper card insertion is insured by detecting the presence of a low level on the pin detect (pnd1, pnd2) inputs, which should be located on opposite ends of the bus connector. these pin detect inputs have internal pull-up resistors and the connection on the host platform side must be connected directly to ground. [in a compactpci application these are the bd_sel# signals]. the pnd inputs have an internal noise filter nominally set at 150ms. once the proper card insertion has been detected, the s39421 will check the status of the hst_pwr signal from the host. implementation of hst_pwr is optional; e.g. it can be used to power down individual cards on the bus via software control. if it is not used by the host system the input must be held high in order for the s39421 to enable power sequencing to the card. once these basic conditions are met the s39421 will begin the power-up portion of the sequence. first, the host platform supplies are checked for compliance. based on the state of the vsel input the s39421 will monitor the +5v and +3.3v supplies. if these are above the vtrip thresholds the sequencing next begins the backend logic power-on operation. the s39421 will drive the vgate3 and vgate5 outputs to the 12v rail to turn on the external 3 volt and 5 volt power fets. the slew rate of these outputs defaults to 250v/s. different slew rates can be accommodated by either adding an additional capacitor between the fet gate and ground or by injecting current into the islew input. reset control in order to provide positive control to an add-in-card ? s bakckend logic, the reset control function of the s39421 begins operation as soon as a voltage is applied to vcc5. the conditions that affect the reset outputs are the vcc5, vcc3, card_5v and card_3v input levels and the state of the hst_rst input. assume hst_rst has been released and is pulled high. the s39421 reset ouputs will be valid as long as vcc5 is 1v. if any one of vcc5, vcc3, card_5v or card_3v input levels is below its respective vtrip level the reset outputs and card_v_vld output will be driven active. (in the case of the card_v_vld output, the active condition is low but its logical true condition is a release of its open drain output pulled high by an external pull-up) as soon as the vcc5, vcc3, card_5v and card_3v inputs are above their vtrip levels card_v_vld will be released and the internal tpurst timer will be started. the reset outputs will be held active until tpurst has expired and then be released. the hst_rst input is also used to control the reset outputs. a high to low transition on hst_rst will initiate a reset cycle with a duration of tpurst. the reset outputs will remain active for a minimum period tpurst or for the duration of hst_rst active low, whichever is longer. a hst_rst activated reset will not affect the power se- quencing logic. during normal operation, the supply voltages are continu- ously monitored. if the cardside supplies fall below the vtrip levels the reset outputs will be driven active. if the host platform supplies fall below vtrip, the s39421 will immediately assert the reset outputs and disable the highside drivers. power configurations the s39421 can be used in 5v-only, 3.3v-only and mixed voltage systems. for mixed voltage systems, simply connect the appropriate bus and card power inputs as indicated. the vsel pin should be grounded. for systems with a single power supply, connect vcc5 and vcc3 together to the platform host early power line (long pin power supply). also connect card5v and card3v together to the cardside power output of the fet. the state of vsel determines the reset level that will be used to signal card_v_vld. for 3.3v systems, tie vsel to the supply; for 5v systems, tie vsel to ground.
s39421 9 2024 9.0 8/8/00 figure 4. vcc5 1v shut off vgte5 vgte3 drvren pwr_vld sgnl-vld no yes no yes yes no turn on pwr_vld tpurst timeout? release resets turn on no yes pnd1 & pnd2? vsel hi ? assert reset outputs yes host 3volt ok? no yes host 5v & 3v ok? turn-on vgte5 vgte3 drvren no sgnl_vld card 5v & 3v ok? start reset timer 2024 ill6.2
10 s39421 2024 9.0 8/8/00 memory operation the s39421 has a 1024-bit nonvolatile memory intended for use with industry standard microprocessors. the memory is organized as x16, seven 9-bit instructions control the reading, writing and erase operations of the device. the device operates on a single 3v or 5v supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when read- ing data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the memory and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. the format for all instructions is: one start bit; two op code bits and either six address or instruction bits. read upon receiving a read command and an address (clocked into the di pin), the do pin will come out of the high impedance state and, will first output an initial dummy zero bit, then begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). continuous read this begins just like a standard read with the host issuing a read instruction and clocking out the data byte [word]. if the host then keeps cs high and continues generating clocks on sk, the s39421 will output data from the next higher address location. the s39421 will continue incrementing the address and outputting data so long as cs stays high. if the highest address is reached, the address counter will roll over to address 0000. cs going low will reset the instruction register and any subsequent read must be initiated in the normal manner of issuing the command and address. write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a mini- mum of 250ns (t csmin ). the falling edge of cs will start automatic write cycle to the memory location specified in the instruction. the ready/busy status can be determined by selecting the device and polling the do pin. page write assume wen has been issued. the host will then take cs high, and begin clocking in the start bit, write command and 6-bit address immediately followed by the first 16-bit word of data to be written. the host can then continue clocking in 16-bit words of data with each word to be written to the next higher address. internally the address pointer is incremented after receiving each group of sixteen clocks; however, once the address counter reaches xxx x111 it will roll over to xx x000 with the next clock. after the last bit is clocked in no internal write operation will occur until cs is brought low. erase upon receiving an erase command and address, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the auto erase cycle of the selected memory location. the ready/ busy status can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical ? 1 ? state. figure 5. sychronous data timing sk 2024 ill19.0 di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data v alid t sklow
s39421 11 2024 9.0 8/8/00 figure 6. read instruction timing sk 2024 ill20.0 cs di do t cs standby t hz high-z high-z 11 0 a n a n ? 1 a 0 0 d n d n ? 1 d 1 d 0 t pd0 erase/write enable and disable the memory powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all s39421 write and clear instruc- tions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the s39421 can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. figure 7. write instruction timing sk 2024 ill21.0 cs di do t cs standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew
12 s39421 2024 9.0 8/8/00 figure 8. erase instruction timing figure 9. ewen/ewds instruction timing sk 2024 ill22.0 cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0 sk 2024 ill23.0 cs di standby 10 0 * * enable=1 1 disable=00 figure 10. wral instruction timing sk 2024 ill24.0 cs di do t cs high-z 10 1 busy ready status verify t sv t hz t ew 0 0 standby d o d n
s39421 13 2024 9.0 8/8/00 instruction set instruction start opcode address data comments bit x16 x16 read 1 10 x(a5 ? a0) read address an ? a0 erase 1 11 x(a5 ? a0) clear address an ? a0 write 1 01 x(a5 ? a0) d15 ? d0 write address an ? a0 ewen 1 00 11xxxx write enable ewds 1 00 00xxxx write disable wral 1 00 01xxxx d15 ? d0 write all addresses 2024 pgm t5 .0 figure 11. data downloader sequence of operation [note: all data download timing conforms to the timing shown in figure 5] data download mode the data download mode is an alternative method of accessing the e 2 prom memory. use of this mode allows downloading the entire contents of the memory without entering any commands. the dd mode is enabled after a low to high transition on the dd pin, while continuing to assert dd (this includes powering up the device with dd tied high). also, as a condition to enter this mode, the device must not be in a state of reset. once in data download mode, the device will wait until chip select is driven active. at this point, the device will output a dummy ? 0 ? followed by the contents of location 0000. as long as the sk line is toggled the s39421 will continue to output the contents of sequential address locations. in this manner, the configuration data that is loaded into an interface device can be accessed in a simple manner without requiring the logic of the interface chip to generate the complex signals needed for the microwire interface. data download mode is exited upon the first high to low transition of the chip select input. data from address 000 data from address 001 data from address 1fe data from address 1ff do sk cs dd vcc dummy 0 2024 ill7.1 dd mode disabled dd mode enabled after reset is released and after dd is taken to logic 1 reset
14 s39421 2024 9.0 8/8/00 data download control there are a number of ways to implement the data download mode of operation. for applications that do not require use of this feature, simply ground the dd pin and disable the function altogether. reset dd system reset 2024 ill8.0 figure 12. dd disabled figure 14. asic control figure 13. one time download reset dd cs sk do di asic i/oa i/ob i/oc i/od i/oe reset 2024 ill10.0 in figure 13, dd is tied to v cc through a pull-up resistor. this will allow only a single download after power on. the actual download function would not be enabled until t purst had expired and cs was brought high. as soon as cs is deselected the dd mode will be disabled. the primary disadvantage to this method is the lack of a reload after brownout. the dd mode may or may not be initiated depending on how low the power is cycled. in figure 14, the s39421 dd mode is 100% under the control of the add-in board ? s asic. the pull-down resistors insure cs and dd do not float while the asic is in a reset state or shortly thereafter, which may lead to spurious activity on cs and dd, possibly indicating a false dd request. system reset reset dd 2024 ill9.0
s39421 15 2024 9.0 8/8/00 reset dd cs sk do di asic i/oa i/ob i/oc i/od i/oe reset 2024 ill11.0 figure 15. download enabled in conjunction with reset release figure 15 is a good implementation to use whenever there is a requirement to download data from the memory after any reset cycle. this provides control of the dd input function after power-on, brown-out or a system induced reset condition. in this way the data download function is ready under any circumstance an asic or mcu might need to reload initialization data. data from address 000 data from address 001 data from address 1fe data from address 1ff do sk cs dd vcc dd mode enabled dummy 0 reset dd mode disabled 2024 ill12.0 figure 16. dd circuit 4 timing sequence diagram
16 s39421 2024 9.0 8/8/00 slew rate control the nominal slew rate for the vgate3 and vgate5 outputs is set at a default value of 250v per second, which conforms to a number of standards including that for compact pci. this slew rate helps limit current spike transients as the bypass capacitors of the add-in card are charged. the conditions for the default slew rate are: islew input is grounded; and the c vgate capacitance is less than or equal to 0.08f. the slew rate can be extended (made slower) by adding capacitance to the vgate outputs. in this case it should be assumed the i slew input is grounded. the vgate outputs can drive up to 20a typically, so the slew rate may be calculated as 20a c vgate (not exceeding 250v/s). refer to graph 1 shown below. 300 250 200 150 100 50 0 0 0.1 0.2 0.3 0.4 slew rate (v/s) capacitance ( f) 2024 ill13.0 the slew rate can be increased (made faster) by injecting current into the islew input. one quarter of the current injected into islew will be mirrored out of the vgate drivers. the resulting slew rate may be calculated as i slew 4xc vgate (not less than 250v/s). example slew rates are plotted to illustrate the effects of capacitance on the vgate output in graph 2. the reason for the flat portion of the graph is that the internal slew rate control operates in parallel to add as much as 20a (typically) to help keep the sr at 250v/s. note that the islew input is simply a diode-connected mosfet. as a consequence, its i-v characteristic is temperature dependent. 1200 1000 800 600 400 200 0 0 100 200 300 400 slew rate (v/s) 250v/s 2024 ill15.0 c = 0.2 f i slew current in a c = 0.08 f figure 17 figure 18 figure 19 host 5v to card 5v vout5 vgte5 c vgate i slew 3 23 22 s39421 islew in 2024 ill14.1 10 ?
s39421 17 2024 9.0 8/8/00 56k ? 47nf 47nf gnd 56k ? vgate5 vgate3 s39421/4 to 5v mosfet to 3v mosfet 2024 ill25.0 card power-down the s39421 provides a turn-on slew-rate of 250v/s and a fast turn-off performed by internally shorting the vgate3 and vgate5 outputs to ground. if the card circuitry or host power supply cannot accept a fast shutdown then a cr time constant may be added as shown below. the resistors in series with the 47nf(x7r) capacitors increase the discharge time of the mosfet gates. the values shown provide a shutdown slew of ~5v/ms. decreasing the resistor values increases the shutdown slew-rate, and vice-versa. the capacitor values may also be increased but this will decrease the 250v/s turn-on slew-rate. figure 20. power-down ramp rate control
18 s39421 2024 9.0 8/8/00 boosting reset output drive the slew-rate of the reset output is >30v/s at the lo to hi logic transition with a 50pf load and a 1.5k y pull-up resistor. if the reset output needs to drive a larger load capacitance or needs to slew faster, then an external npn transistor or n-channel mosfet must be added to boost output current. the reset output drives the external transistor providing a current sink capability of >30ma on the reset output. using the boost circuit with a 430 y pull-up resistor and 100pf load capacitance, the slew- rate increases to >50v/s. see diagrams below. s39421 - circuits to increase reset output drive 10k ? 3.9k ? reset reset s39421/4 2n3904 gnd 4.7k ? reset reset s39421/4 tn0200t gnd 2024 ill26.0 figure 21. reset current boost circuit
s39421 19 2024 9.0 8/8/00 figure 22. typical interface schematic +5v +12v +3.3v gnd pci_rst# bd_sel2# bd_sel1# vcc5 pnd2 pnd1 cs sk do di hst_pwr vsel g d 47nf 10 ? s hst_rst vgate5 vgate3 drvren card_v_vld sgnl_vld board 5v board 3.3v board 12v card_5v card_3v vcc12 s s d g g d gnd 3volt pci interface asic reset reset card reset card reset 47nf 47nf * 10 ohm resistors must be located as close as possible to the mosfets. 1k ? dd +5v gnd gnd gnd gnd bus switch early & back end gnd early power back end power healthy# 2024 ill16.7 10 ? 10 ? * * *
20 s39421 2024 9.0 8/8/00 figure 23. +12v and -12v control host bus 5v vcc5 drvren host -12v bus host +12v bus to backend +12v s39421 to backend -12v 2024 ill17.5 1.5k ? 0.1 f 4.7k ? 330k ? 330k ? 4.7k ? p-channel power mos fet s d g 0.1 f 1n4148 0.33 f 1n4148 0.33 f s d g * * 1n4148 n-channel power mos fet 10 ? 10 ? * 10 ohm resistors must be located as close as possible to the mosfets.
s39421 21 2024 9.0 8/8/00 using the s39421 as the primary control circuit on a vme live insertion card high availability is a key feature of many types of systems today. whether the system is a central office switch, a private branch exchange or a server it is important the system stay up and running while adding new services (add-in cards) or replacing faulty boards. therefore, a means for inserting and removing cards while the entire system is powered-on (live) is a necessity. live insertion poses a number of challenges for the add- in card designer. for live insertion to be trouble free we first need to prevent damage to components on the add- in card due to improper supply sequencing. secondly, voltage drop on the system power busses must be pre- vented in order to avoid unwanted system reset condition. lastly, the integrity of the system ? s signals needs to be maintained when additional circuitry is connected to the bus. based upon the proposed live insertion system require- ments the s39421 is an ideal candidate as the add-in card ? s live insertion controller. sequencing the voltages the proposed live insertion specification (see references) outlines 26 operational steps during the insertion of a card. these are broken down into two major categories; the ? insertion process ? and the ? typical board recogni- tion process. ? the first 6 steps have to do with the insertion of the card and sequencing the discharge of any voltage potentials so that by the time the board is ready to make contact with the backplane no esd discharges will occur. even though the balance of the actions tend to overlap they can be viewed as two operations: the add-in card/backend logic sequencing and the backplane/add-in card interface se- quencing. add-in card/backend logic sequencing the process of electrical insertion begins with the contact of special ground and voltage pins. these are longer than the signal and power pins and they are physically located at opposite ends of the connector. the voltage pins are labeled vpc (pre-charge voltage), this is the backplane ? s 5 volt supply and the intent is for this voltage to be used to power the sequencing circuitry, any asics that inter- face to the bus and to pre-charge the ? bus-side ? lines of the signal transceivers. the pc board should be laid out so that ground is routed to all circuits, i.e. grounds should not be linked via the pcb connector. vpc should be tied directly to the vcc5 pin on the s39421 and the device will immediately begin driving its backend circuit control signals [sgnl_vld, card_v_vld, reset and reset] and it will place the voltage ramp control signals [vgate3, vgate5 and drvren] in the off state. the next step is for the controller to recognize that the board is properly seated in the connector. vme has an optional feature that lends itself ideally to this step of the operation; the ejector handles can be used to activate a switch when they are fully rotated and locked. switch closure can be used as the pnd1 and pnd2 inputs on the s39421. the pull-up resistor used for this implementation must be tied to vpc because the backend voltages will not yet have been switched on by the s39421. figure 24: illustration of card injector/ejector switch circuit pnd1 vpc s39421 ejector and switch open pnd1 pulled high vpc pnd1 s39421 card seated ejector locked and pnd1 driven to gnd 2024 ill27.0
22 s39421 2024 9.0 8/8/00 the board ? s pins should now be mated with the backplane connector which in turn will bring the host li/i* and reset* signals to the s39421. these signals should be tied to the device ? s hst_pwr and hst_rst inputs respectively. whenever hst_pwr is low the outputs controlling the backend power on sequencing will be inhibited; it does not impact the reset outputs or reset timer. when low, the hst_rst input will force the reset outputs active; once it is released the reset timer will be started and it will keep the reset outputs active for t purst . at the same time the signal pins are making contact, the backend voltages are applied to the card (3.3v, 5v, +12v and -12v on short pins), but, they are blocked by fets under the control of the s39421 (see figure 3 ). depending upon the state of the vsel pin, the s39421 will monitor either the bussed +5v only, the bussed +3.3v only or both the bussed +5v and +3.3v. once the s39421 has deter- mined these supply voltages are at or above vtrip, (and li/ i* has released hst_pwr) it will release the vgate outputs and effectively turn them on at a rate equivalent to 250v/second. at the same time it will force drvren active thus providing power to the backend circuits. figure 25: general block diagram of s39421 host bus interface and backend signal interface vgate3 vgate5 drvren reset reset pnd1 gnd gnd vpc vpc sgnl_vld hst_rst hst_pwr card3v card5v li/o* il/i* reset* backend power circuits see figure backend voltage to s39421 monitor circuits reset control of backend circuits ejector switch circuit s39421 system vcc vcc5 2024 ill28.0
s39421 23 2024 9.0 8/8/00 the s39421 will now begin monitoring the backend circuit voltages and when they are at or above vtrip the reset timer will be released to begin the time out period and card_v_vld will be released. after tpurst has ex- pired, the reset outputs will be released and sgnl_vld will be driven active. the sgnl_vld signal can be tied to the host li/o* signal pin to indicate the card has been fully powered, cleanly reset and is ready for action. backplane/add-in card sequencing a more complicated problem than the sequencing shown above is the signal bus interface. inserting unpowered circuits onto the signal bus could lead to a situation of damaging components and much more likely disrupting the signals on the backplane. this will involve a rigorous evaluation and selection process by the design engineer to determine the best solution for the individual applica- tion. however, we can examine a product family that should resolve most of the issues the designer might encounter. the proposed vme live insertion spec actu- ally helps us narrow this down quickly by recommending the use of abte logic. this is available from at least two large manufacturers of semiconductors. avoidance of bus conflicts bus conflicts arise when two or more interface circuits attempt to drive the bus simultaneously with one circuit driving high and the other driving low. the device trying to drive low will most likely not incur damage. but the device trying to drive high will be dropping 5volts on its output at up to 120ma current. even for very short periods of time the high temperatures this will generate can either destroy the device or adversely affect the long-term reliability of the device. the best solution is to insure the transceiver ? s enable input is actively driven before the transceiver is powered-on. using one of the reset outputs (as shown in figure 27) as a gating signal to a single enable input style transceiver is one solution. with a dual enable transceiver one of the reset outputs can be tied directly to appropriate enable input. figure 26: backend voltage control circuit -12v +12v +3.3v +5v gnd vpc gnd vpc vcc5 vcc12 vgate3 vgate5 drvren islew card_3v card_5v vsel backend circuitry +5v +3.3v -12v +12v s39421 2024 ill29.3
24 s39421 2024 9.0 8/8/00 pre-bias the switching capacitance of the individual signal lines at the interface must be charged to the instantaneous volt- age on the corresponding bus line. these currents distort the signal that is being transmitted at that instant. to address this issue the proposed vme live insertion spec states: ? all vme system drivers and receivers shall be pre-biased to 1.7 =/-0.2 vdc with a resistive network powered by the pre-charge +5v. . . before the board signal pins contact the backplane vme64 bus connector(s). ? the abte logic addresses this issue head-on by provid- ing a separate vccbias pin that is internally connected to a pre-charge resistor network. card removal a clean transition for card removal can be performed either by the opening of the injector/ejector levers which in turn opens the switches that force the pnd inputs to ground or by the host driving li/i* low. both actions will tell the s39421 to disable the high side drivers and force the reset outputs active. recap as the board is first inserted into the backplane voltage potentials on are shunted to ground thru the use of various bleed resistors and physical contact with the chassis frame. these are make then break processes so that by the time the card is ready to make contact with the backplane connector the board is electrically isolated from the frame. the first pins of the connector to make contact with the backplane are ground and vpc (pre-charge vcc). vpc should be tied directly to the s39421 and the transceiver biasvcc input. once the s39421 detects the presence of vpc it will begin driving the reset outputs active, shut off all the control signals to the power fets and begin driving the li/o* low. the injector/ejector levers will close the switches grounding the pnd inputs allowing the s39421 to check the state of the vsel pin and determine what bus voltages should be monitored. if the bus voltages are at or greater than vtrip and li/i* has been released the s39421 will turn on the high side driver outputs vgate3 and vgate5 and the drvren output. the voltages to the backend logic are applied with a nominal slew rate of vgate3 and vgate5 set at 250v/ sec. the backend voltages should also be fed back to the s39421 and as soon as they are at or above their vtrip level, the card_v_vld will be released. if the host has released its reset input and li/i* input, the s39421 will release the timer for its reset circuit. after tpurst the reset outputs to the backend logic will be released and the sgnl_vld output will be driven active [backplane signal li/o]. this is the final step in activating a board for live insertion.
s39421 25 2024 9.0 8/8/00 figure 27: a bus interface solution vpc vcc5 gnd gnd hst_pwr li/i* reset vpc gnd vccbias gnd vcc sgnl_vld li/o* drvren vgate3 vgate5 card_5v card_3v hst_rst oe abte245 s39421 to add-in card back-end voltage ramp circuits add-in card backend circuitry card-oe d-1 d-2 d-32 d-31 2024 ill30.1
26 s39421 2024 9.0 8/8/00 appendix a mosfets suitable for use with the s39421 hot-swap controller n-channel mosfets part number manufacturer v(br) dss r ds(on) @ v gs =10v i d cont. package irf7603 int. rectifier 30v 35 milliohms max 4.5a micro-8 irf7413 int. rectifier 30v 11 milliohms max 9.2a so-8 mtsf3n03hd motorola 30v 40 milliohms max 3a micro-8 mmsf7n03hd motorola 30v 28 milliohms max 8a so-8 mtd20n03hdl2 motorola 30v 35 milliohms max 20a dpak si6434dq temic 30v 28 milliohms max 5.6a tssop-8 si6410dq temic 30v 14 milliohms max 7.8a tssop-8 si4412dy temic 30v 28 milliohms max 7a so-8 si4416dy temic 30v 18 milliohms max 9a so-8 p-channel mosfets part number manufacturer v(br) dss r ds(on) @ v gs =10v i d cont. package irf7606 int. rectifier -30v 90 milliohms max 2.9a micro-8 irf7416 int. rectifier -30v 20 milliohms max 7.1a so-8 mtsf2p03hd motorola -30v 90 milliohms max 2.4a micro-8 mmsf3p02hd motorola -20v 75 milliohms max 3a so-8 mtd20p03hdl2 motorola -30v 99 milliohms max 19a dpak si6435dq temic -30v 90 milliohms max 4.5a tssop-8 si6415dq temic -30v 19 milliohms max 6.5a tssop-8 si4431dy temic -30v 40 milliohms max 5.8a so-8 si4435dy temic -30v 20 milliohms max 8a so-8 references: vita standards organization, november 1997, vme64x live insertion system requirements draft standard summit microelectronics, inc. s39421 data sheet texas instruments application note sdya012, october 1996, live insertion
s39421 27 2024 9.0 8/8/00 24--lead small outline package (soic) ordering information 0.014 - 0.019 (0.356 - 0.482) 0.004 - 0.012 (0.102 - 0.305) 0.037 - 0.045 (0.940 - 1.143 0.596 - 0.612* (15.20 - 15.49) 0.394 - 0.419 (10.00 - 10.65) 0.093 - 0.104 (2.362 - 2.642) 0.016 - 0.050 (0.406 - 1.270) 0.050 (1.270) 0.009 - 0.013 (0.229 - 0.330) 0.010 - 0.029 (0.254 - 0.737) 0.291 - 0.299 (7.391 - 7.595) 24pn soic ill.0 x45 0 to 8 typ package s = 24 lead soic base part number s39421 s 2024 ill18.0
28 s39421 2024 9.0 8/8/00 notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2000 summit microelectronics, inc.

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